1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of producing a semiconductor device comprising at least a bipolar transistor. The present invention is preferably applied to the production of a semiconductor device comprising a bipolar transistor and a metal-oxide-semiconductor field effect transistor (MOSFET).
2. Description of the Related Art
A semiconductor device comprising a bipolar transistor and MOSFET has been produced on the same chip by a bipolar MOS (Bi-MOS) technology (see, e.g., Y. Okada et al: "ABC--An Advanced Bipolar-CMOS VLSI Technology," Extended Abstracts of 16th Conference on Solid State Devices and Materials, A-5-3, 1984, pp. 229-232, and A. R. Alvafez et al, "2MICRON MERGED BIPOLAR-CMOS TECHNOLOGY," IEDM, Tech Dig. pp. 761-764, 1984).
In general, interconnections including the electrodes of a bipolar transistor and the source and drain electrodes of a MOSFET are made of a metal layer of aluminum (Al) or alloy thereof, and these electrodes are formed with an insulating layer so that they are buried in electrode contact windows formed in the insulating layer. The insulating layer over a polycrystalline silicon gate which has these electrode contact windows, has a step-like portion, which can cause a break in the interconnections, resulting in a device failure or a formation of a thin portion thereof which reduces the reliability of the device. Also so-called stepcoverage defects of the metal layer (interconnections) occur. To eliminate the above disadvantages, the step-like portion of the insulating layer under the metal layer is gently sloped, i.e., the surface profile of the insulating layer is flattened, and this sloping or flattening contributes to a miniaturization of the pattern of the interconnections. Therefore, for flattening the insulating film, the insulating layer is made of an impurity-containing glass, such as phosphosilicate glass (PSG) and then the device is heated at a high temperature of, e.g., 1000.degree. C., so that the glass layer is softened and made to flow, i.e., a so-called glass flow occurs.
When the glass flow technique is used for the insulating layer under the metal layer, a semiconductor device comprising, for example, an npn bipolar transistor and an n-channel MOSFET is produced in the following manner.
An n-type epitaxial silicon layer is formed on a p-type silicon substrate, and a p-type isolation region for the bipolar transistor and a p-well (p-type region) are simultaneously formed in the n-type epitaxial layer. An n-type contact layer is formed in the epitaxial layer portion surrounded by the isolation region, and the epitaxial silicon layer is selectively and thermally oxidized to form a thick oxide (SiO.sub.2) insulating layer. The epitaxial silicon layer except for the already oxidized portion is then oxidized to form a thin oxide (SiO.sub.2) insulating layer (a gate oxide layer). A polycrystalline silicon gate electrode is formed on the gate oxide layer, and donor impurities are ion-implanted into the p-well through the thin oxide insulating layer, in self-alignment with the gate electrode and the thick oxide insulating layer, to form an n-type source region and an n-type drain region. Acceptor impurities are ion-implanted into the isolated epitaxial silicon layer through the thin oxide insulating layer in self-alignment with the edge of the thick oxide insulating layer, so that a p-type base region is formed, and the thin oxide insulating layer is then selectively etched to open a collector contact window and an emitter contact window. A polycrystalline silicon layer is deposited and is patterned to cover the windows, respectively. The formation of the polycrystalline silicon layer prevents spiking of the aluminum alloying with silicon. Donor impurities are ion-implanted into the collector contact region and the base region through the polycrystalline silicon layer in the contact windows, respectively, to form an n-type contact region and an n-type emitter region, respectively. The PSG layer is then formed on the whole surface, including the gate electrode surface, and is flattened by a heat-treatment producing a glass flow. Note, since the PSG layer covering the gate electrode has undesirable step-like portions, the production process of the Bi-MOS technology includes an indispensable step of sloping and flattening the PSG layer. The PSG layer is selectively etched to open electrode contact windows (i.e., collector, emitter, base, source, drain, and gate electrode contact windows), and Al or Al alloy is then deposited on the whole surface and is patterned to form electrodes (i.e., collector, emitter, base, source, drain and gate electrode) and interconnections, and as a result, the desired semiconductor device is produced.
In the above process, a high temperature of, e.g., 1000.degree. C., is used for the heat-treatment needed to cause the PSG flow (i.e., the flattening or smoothing of the PSG layer), but this high temperature causes an overdiffusion of donor impurities forming the emitter region. This causes an undesirable expansion of the emitter region with a corresponding variation in a current amplification factor: i.e., the current amplification factor of the bipolar transistors of the obtained semiconductor devices is uneven. Furthermore, a window opening step for the emitter of the bipolar transistor must be carried out twice, and if the alignment of the window position in the second window opening step in which the PSG layer is selectively etched is not correct, the portion of the thin oxide insulating layer adjoining the emitter region and outside the polycrystalline silicon layer on the emitter region may be etched during the PSG layer etching. In this case, when the metal layer for the emitter electrode is deposited, the metal layer causes a short circuit between the emitter and base. To prevent this defect, the dimensions of the polycrystalline silicon layer covering the emitter region must be made larger, While taking into consideration the alignment tolerance in the second window opening step. Accordingly, the distance between the emitter electrode and the base electrode must provide a sufficient margin. However, such an increase in the polycrystalline silicon layer area and the margin obstruct any intended miniaturization of the device.